In sdram_config.scr we read:
// SDRAM timing-fix
PROCESSOR TarReTAP = { no}
PROCESSOR TarResLo = { 50ms}
PROCESSOR TarResHi = { 50ms}
RESET TARGET
%v = DWORD AT 0x00100070
DWORD AT 0x00100070 = %v
DWORD AT 0x0010002c = 1
DWORD AT 0x0010002c
DWORD AT 0x00100180 = 0x00074777
DWORD AT 0x00100184 = 0xffc3ffff
// END-SDRAM timing-fix
1)which is the function of these registers(Can't find them in Program Reference Guide)?
2)my sdram-check works fine with compiler optimization level 0 and 1, but rising compiler optimization(in HITOP) I have problem in sdram data integrity: it fails always at same address and bit REFRESH_ERROR in MEM_SDRAM_CFG_CTRL is asserted, though using REFRESH_MODE(same register) set to 0, fixed at 15.60us as my sdram's datasheet tells.
I tried to configure sdram registers with cautious value too and insert delays between readings, but no change.
Something related with "SDRAM timing-fix"?
M T
Hilscher Gesellschaft für Systemautomation mbH
1)
These registers modify some of the internal Priorities of the netX. Most of these settings can only be done after a systemreset, before any program starts. So executing them out of your program will not work. (That's why they are executed right after the reset command).
2)
Please use the recommended Refresh Mode of 3 (Collect 2048...), which comes from the SDRAM Standards Specification.
Please try activating the Instruction Cache, as this will reduce the SDRAM load caused by the ARM core, and let's the SDRAM controller do it's refreshes without being interrupted by the ARM too often.
Regards
MT