My project faces a problem:
Suddenly, Master have 5 Bytes (different each other) to send to each slave(3 slaves in all).
If through the cyclic time Data channel, the sudden data will be delayed at least the minimal cyclic time (i.e.:Sercos III--250us ; Ethernet/IP--1000us).
Nervertheless,
Sending these sudden data through acyclic channel, will the delay be shorter? For example, Ethernet/IP
Hello houzenan,
you should know, that acyclic services are significant slower as cyclic services.
E. g. in SERCOS the master needs at least two steps (open an IDN and read/write the data). Each steps usually takes multiple bus cycles because of the reaction time in slave and master. The transfered data in one bus cycle is limited to 4 bytes.
Johnny
Thank you
However, ProfiNet IO use "RTA Real time Acyclic Protocol" to send immediate data.
Right?
That is partially true.
RTA is only used for Alarm frames (e.g. Process alarms and Diagnosis Alarms). Normally RTA is used unidirectional from IO-Device to the IO-Controller. This frames use a 2way handshake on the bus and is quite fast/immediate.
The acyclic communication (Read / Write Record) uses UDP-based RPC frames. This is bidirectional. It is definitively slower as more layers are involved (UDP, RPC, ContextManagment).
Real-time Ethernet is slower than point-to-point RS422 (that is RS422 at 10Mbps and full-duplex).
Right?
Hey,
why don't you use EtherCAT. Nothing is faster then this. I don't know which frequency the Hilscher master supports buts it some masters can do about 20Khz. In this way you are able to update your data every 50us. Jitter should be under 1us if you use a RT-OS.
Hi,
that is why synchronization in buses like Sercos III and EtherCAT exists, the bus cycle delay and jitter is not anymore involved. Therefore, the data activation and bus cycle will not anymore interact.
The bus cycle is typically determined by the master which must be capable of handling the required bus cycle.
Acyclic channels are not bound to predictable latencies. Therefore, you can gain even higher latencies than the actual bus cycle is.